Contained within the directory big_flat_stru are the component
realizations of the behavioral descriptions contained within big_flat_beh.
Each different description under form7.vhd up to form14.vhd represent
7 input up to 14 input parity generators.  Each description was
generated by taking the concurrent signal assignment statement expanded
in the appropriate formN.vhd file (where 6 < N < 15), searching down
the operator tree, and gnerating components with new interconnecting
signals.  Each of the descriptions are characterized by their size
below.


NAME       |  components  |  signals  |  sgnl asgmnt stmnts | assertions
------------------------------------------------------------------------
 form7.vhd |     315      |    324    |          3          |     1
 form8.vhd |     635      |    645    |          3          |     1
 form9.vhd |    1275      |   1286    |          3          |     1
form10.vhd |    2555      |   2567    |          3          |     1
form11.vhd |    5115      |   5128    |          3          |     1
form12.vhd |   10235      |  10249    |          3          |     1
form13.vhd |   20475      |  20490    |          3          |     1
form14.vhd |   40955      |  40971    |          3          |     1
form15.vhd |   81915      |  81932    |          3          |     1


The components used are declared as follows:


            component inverter
                    port ( input : in bit;
                           output : out bit);
                end component;
         for all : inverter use entity work.inverter( inverter );
            component and_gate
                    port ( in1 : in bit;
                           in2 : in bit;
                           output : out bit);
                end component;
         for all : and_gate use entity work.and_gate( and_gate );
            component or_gate
                    port ( in1 : in bit;
                           in2 : in bit;
                           output : out bit);
                end component;
         for all : or_gate use entity work.or_gate( or_gate );

Each component's architecture contains one concurrent signal assignment
statement.

    For a signal assignment statement that looks like:

    out1 <= (not(a) and b) or (a and not(b)) after 5 ns;

the derived components and signal assignment statement would look like

    out1 <= n5 after 5 ns;
inv_1: inverter
    port map (input => a,
              output => n1);
and_2: and_gate
    port map (in1 => b,
              in2 => n1,
              output => n2);
inv_3: inverter
    port map (input => b,
              output => n3);
and_4: and_gate
    port map (in1 => a,
              in2 => n3,
              output => n4);
or_5: or_gate
    port map (in1 => n2,
              in2 => n4,
              output => n5);

The necessary signal declarations are also made.
