----------------------------------------------------------------------
-- Module name:     VMEPCIBR_SOCv.TXT
--
-- Description:     Test vectors used by the VMEPCIBR_SOCt.VHD test
--                  bench.
--
-- File History:    Project complete:       WD Peterson - 25 JUN 2002
--                  Add 'BUF_H' tests:      WD Peterson - 25 JUL 2002
--                  Add CEEPROM tests:      WD Peterson - 04 SEP 2002
--                  Change EEPROM clock en: WD Peterson - 08 OCT 2002
--                  LGPL licensing:         WD Peterson - 17 JAN 2004
--
-- License:         Copyright (C) 2002 Silicore Corporation
--
--                  This library is free software; you can
--                  redistribute it and/or modify it under the terms
--                  of the GNU Lesser General Public License version
--                  2.1 as published by the Free Software Foundation.
--
--                  This library is distributed in the hope that it
--                  will be useful, but WITHOUT ANY WARRANTY; without
--                  even the implied warranty of MERCHANTABILITY or
--                  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--                  Lesser General Public License for more details.
--
--                  You should have received a copy of the GNU Lesser
--                  General Public License along with this library;
--                  if not, write to the Free Software Foundation,
--                  Inc., 59 Temple Place, Suite 330, Boston, MA
--                  02111-1307  USA
--
--                  US Government rights: this software was produced
--                  for the US Government under Contract No.
--                  DAAE30-95-C-0009 and is subject to the Rights in
--                  Noncommercial Computer Software and Noncommercial
--                  Computer Software Documentation Clause (DFARS)
--                  252.227-7014 (JUN 1995).  The Licensee agrees that
--                  the US Government will not be charged any license
--                  fee and/or royalties related to this software.
--
-- Support:         Support for this software in the form of
--                  maintenance, system integration, consulting and
--                  training is available for a fee from Silicore
--                  Corporation.  For more information please refer
--                  to the Silicore web site at: www.silicore.net.
----------------------------------------------------------------------

------------------------------------------------------------------------------------
--                        Test Vector Nomenclature
--
-- 'U' -> Uninitialized
-- 'X' -> Forcing unknown
-- '0' -> Forcing 0
-- '1' -> Forcing 1
-- 'Z' -> High impedance
-- 'W' -> Weak unknown
-- 'L' -> Weak 0
-- 'H' -> Weak 1
-- '-' -> Don't care
--
-- 'T' -> Three-state signal
-- '*' -> Indicates that output state is ignored.
--
------------------------------------------------------------------------------------------------------------------------------------------------------------
--     |           VMEbus Inputs             |      PCI Inputs      |Control| C |     |  VMEbus Outputs  |     PCI Outputs      |Control|CEEPROM|
--     |-------------------------------------|----------------------|-------|---|     |------------------|----------------------|-------|-------|
--     |                                     |                      |   N   |   |     |                  |                      |   N   |       |
--     |                       N             |                      |   - N |   |     |                  |                      |   -   | N     |
--     |                       -             |                      |   V - | C |     |                  |                      |   V N | - C C |
--     |                       V             |                      | N S W | O |     |                  |                      |   S - | C O O |
--     |                     N S N           |                      | - Y D | N |     |              N   |                D     | S Y V | O N N |
--     |                   N - Y -           |              F       | V S T | F |     |          N N -   |                E     | P S A | N F F |
--     |               N N - V S V           |              R I     | A F I | S |     |          - - V   |            T S V P S | A F C | F S S |
--     |             N - - V L R W           |              A R I R | C A M | E |     |          V V D N |            R T S E E | R A F | S E E |
--     |             - V V I W E R           |              M D D S | F I E | R |  P  |          D B T - |            D O E R R | T I A | E R R |
--     |             V D D A O S I         V |          C P E Y S T | A L O | D |  C  |          D E A V |          P Y P L R R | A L I | R C D |
--     |     V     G A S S C R E T    V    A |     A    B A - - E - | I - U | A |  L  |     V    I R C O |     A    A - - - - - | N - L | E L A |
-- VEC |     D     A S 0 1 K D T E    A    M |     D    E R N N L N | L I T | T |  K  |     D    R R K E |     D    R N N N N N | 1 O B | N K T |    NOTES
------------------------------------------------------------------------------------------------------------------------------------------------------------
--     | TTTTTTTT II I I I I I I I IIIIII II | TTTTTTTT I T I I I I | I I I | T |  I  | TTTTTTTT O O O O | TTTTTTTT T O O O O O | O O O | O O T |
------------------------------------------------------------------------------------------------------------------------------------------------------------

-- Apply the VMEbus and PCI resets.  This initializes the EEPROM interface clock divider.
                                    
: 2000   ZZZZZZZZ 00 1 1 1 1 1 0 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 0   1 1 1   H   CLK   ******** * * * *   ******** * * * * * *   * * *   * * *  -- Apply resets
: 2001   ZZZZZZZZ 00 1 1 1 1 1 0 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 0   1 1 1   H   CLK   ******** * * * *   ******** * * * * * *   * * *   * * *  -- Apply resets
: 2002   ZZZZZZZZ 00 1 1 1 1 1 0 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 0   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   1 1 1   1 Z H  -- Apply resets
: 2003   ZZZZZZZZ 00 1 1 1 1 1 0 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 0   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   1 1 1   1 Z H  -- Apply resets
: 2004   ZZZZZZZZ 00 1 1 1 1 1 0 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 0   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   1 1 1   1 Z H  -- Apply resets

: 2005   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2006   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2007   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2008   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2009   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --


-- Clock the EEPROM interface twice to initialize all internal state machines (84 x 2 PCLKs).

: 2010   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2011   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2012   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2013   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --


-- Verify that the reset bit is cleared by doing a VMEbus read from CEEPROM 'CONFIG_PROM_CMD' register at 0x00004.

: 2020   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2021   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2022   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 0 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2023   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 0 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2024   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   00000800 0 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2025   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   00000800 0 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2026   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   00000800 0 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2027   ZZZZZZZZ 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
    

-- Use the manual configuration override function to twiddle the output bits.

: 2030   00000180 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2031   00000180 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2032   00000180 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2033   00000180 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2034   00000180 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2035   00000180 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2036   00000180 15 1 1 1 1 1 1 1 FFFFFF 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2037   00000180 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --

: 2038   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2039   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 203A   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 0 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 203B   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 0 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 203C   ZZZZZZZZ 15 0 0 0 1 0 1 1 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   00000180 0 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 203D   ZZZZZZZZ 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --

: 203E   00000380 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 203F   00000380 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2040   00000380 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2041   00000380 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --
: 2042   00000380 15 1 1 1 1 1 1 1 FFFFFF 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --
: 2043   00000380 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --

: 2044   00000780 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --
: 2045   00000780 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --
: 2046   00000780 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --
: 2047   00000780 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --
: 2048   00000780 15 1 1 1 1 1 1 1 FFFFFF 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 H  --
: 2049   00000780 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 H  --


-- Send a start condition.

: 2050   00000000 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 H  --
: 2051   00000000 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 H  --
: 2052   00000000 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 H  --
: 2053   00000000 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 H  --
: 2054   00000000 15 1 1 1 1 1 1 1 FFFFFF 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2055   00000000 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --

: 2056   00000082 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2057   00000082 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2058   00000082 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 2059   00000082 15 0 0 0 1 0 1 0 280002 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 0 0   ZZZZZZZZ Z H H H H H   * 1 1   1 Z H  --
: 205A   00000082 15 1 1 1 1 1 1 1 FFFFFF 3D   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 H  --
: 205B   00000082 15 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   CLK   ******** 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 H  --

: 205C   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 H  --

: 205D   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 1  --
: 205E   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 1  --
: 205F   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 1 0  --
: 2060   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 0  --

: 2061   ZZZZZZZZ 00 1 1 1 1 1 1 1 FFFFFF FF   ZZZZZZZZ Z Z H H 0 1   1 1 1   H   054   ZZZZZZZZ 1 1 1 0   ZZZZZZZZ Z H H H H H   * 1 1   0 0 H  --

